1. Field of the Invention
Generally, the present disclosure relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor devices having metal-silicide portions on semiconductor regions to reduce the resistance of the semiconductor regions.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features are steadily decreased to enhance device performance and functionality. One important circuit element in complex integrated circuits is a field effect transistor, which represents a component having a channel region, whose conductivity may be controlled by an electric field that is generated by applying a control voltage to a gate electrode formed near the channel region and separated therefrom by a gate insulation layer. The channel region is generally defined by respective PN junctions formed by an interface of highly doped drain and source regions and an inversely doped region located between the drain and source regions. Important characteristics for the performance of an integrated circuit are, among others, the switching speed of the individual transistor elements and the drive current capability. Thus, one important aspect for obtaining a high transistor performance is the reduction of the overall resistance of the current path defined by the channel region, the resistance of the drain and source regions and the respective contacts that connect the transistor with peripheral devices, such as other transistors, capacitors and the like. The reduction of the channel length thus provides reduced resistance of the channel region and also offers the potential to increase the packing density of the integrated circuit. Upon reducing the transistor dimension, the transistor width is also typically reduced in view of packing density and switching speed, which may, however, reduce the drive current capability. It is, therefore, of great importance to reduce the series resistance of a transistor for given design dimensions as much as possible so as to combine moderately high drive current capability with increased switching speed for sophisticated logic circuits.
Hence, it becomes an important design goal to increase the conductivity of lines and contact regions, such as drain and source regions, gate electrodes, polysilicon interconnect lines and the like, since the cross-sectional area of these lines and regions is also reduced as the general transistor dimensions are decreased. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the resistance of the respective line or contact region. As a result, in highly scaled semiconductor devices, the conductive lines and contact regions may exhibit a higher resistance unless the reduced cross-section is compensated for by improving the electrical characteristics of the material forming the lines and contact regions, such as the gate electrode, and the drain and source contact regions.
It is thus of particular importance to improve the characteristics of conductive regions that are substantially comprised of semiconductor material such as silicon. For instance, in modern integrated circuits, the individual semiconductor devices, such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum by, for example, copper and copper alloys, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact regions is required.
With reference to FIGS. 1a-1b, an exemplary process for manufacturing an integrated circuit containing, for example, a plurality of MOS transistors, will now be described in order to illustrate the problems involved in improving the electrical characteristics of silicon-containing semiconductor regions in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor structure 100 that includes a substrate 101, for example, a silicon substrate above which is formed a field effect transistor 110 of a specified conductivity type, such as an N-channel transistor or a P-channel transistor. The semiconductor structure 100 comprises an isolation structure 113 formed of an insulating material, such as silicon dioxide, silicon nitride and the like, which defines an active region 112 in the substrate 101. In advanced semiconductor devices, the isolation structure 113 may be provided in the form of a shallow trench isolation (STI), filled, at least partially, with one or more appropriate insulating materials, for instance as specified above. A gate electrode 115 having a gate length 115L is formed over a gate insulation layer 118 that separates the gate electrode 115 from the active region 112. Spacer elements 116 made of, for example, silicon dioxide or silicon nitride, are located at the sidewalls of the gate electrode 115. In the active region 112, source and drain regions 114, including respective extensions 114a, are formed and exhibit an appropriate lateral dopant profile required to connect to a channel region 111, in which a conductive channel builds up between the drain and the source regions 114 upon application of an appropriate control voltage on the gate electrode 115. Moreover, metal silicide regions 117 are formed within the drain and source regions 114 and on the gate electrode 115. The metal silicide regions 117 may be comprised of any appropriate metal silicide, based on an appropriate refractory metal, such as titanium, cobalt, nickel, platinum, tungsten or combinations thereof.
FIG. 1b schematically illustrates a top view of the semiconductor structure 100. As shown, the gate electrode 115 extends in the transistor width direction, indicated as W, beyond the active region 112 (the area within the isolation structure 113) into the insulated portion of the substrate 101 defined by the shallow trench isolation structure 113. Depending on the circuit layout, the gate electrode 115 may connect to an adjacent transistor or to a respective contact region (not shown). As previously discussed, the gate length 115L of the transistor element 110 substantially determines the channel length of the transistor 110 and, therefore, as previously pointed out, significantly affects the electrical characteristics of the transistor element 110. The transistor width is defined by the dimension of the active area 112 along the width direction W and is therefore determined by the trench isolation structure 113. For a given gate length 115L determining the resistance per unit length in the direction of current flow and the switching speed, the transistor width also affects the drive current capability. However, as previously explained, in view of packing density and reduced overall switching speed, the transistor width may not be arbitrarily increased.
A typical process flow for forming the semiconductor structure 100 as depicted in FIGS. 1a-1b may comprise the following processes. After the formation of the trench isolation structure 113 by well-known photolithography, etch, deposition and planarization techniques, implantation steps may be performed to create a vertical dopant profile in the active region 112 according to device requirements. Subsequently, the gate insulation layer 118 is formed according to design requirements, after cleaning the exposed surface of the active area 112. Thereafter, the gate electrode 115 may be formed by patterning, for instance, a polysilicon layer by means of sophisticated photolithography and etch techniques. Then, a further implantation step for forming the source and drain extensions 114a within the source and drain regions 114 may be performed, for instance, on the basis of appropriate offset spacers (not shown) and then the spacer elements 116 may be formed by deposition and anisotropic etch techniques. The spacer element 116 may be used as an implantation mask for a subsequent implantation process in which a dopant is implanted into the active region 112 to form the source and drain regions 114, thereby creating the required high dopant concentrations in these regions. Typically, appropriate anneal processes are performed to activate the dopants and to reduce implantation-induced lattice defects. Thereafter, the metal silicide regions 117 may be formed by well-established techniques including, for example, the deposition of a suitable refractory metal and performing a heat treatment in order to initiate a silicidation process. A suitable low ohmic phase may be obtained by a further heat treatment in accordance with established techniques. It should be appreciated that the resulting sheet resistance of the metal silicide regions 117 is significantly less compared to the resistance of the semiconductor materials of the drain and source regions 114 and the gate electrode 115, although these areas are heavily doped. Consequently, by providing the metal silicide regions 117, the reduced cross-sectional area of the contact regions, i.e., the silicided portions of the drain and source regions 114, and polysilicon lines, such as the gate electrode 115, may be compensated for to reduce the parasitic resistance despite the overall reduced transistor dimensions.
In view of a further reduction of the series resistance between the channel region 111 in its conducting state and the surface areas of the metal silicide regions 117, at which respective metal plugs may contact the transistor 110, it would be desirable to increase, for a given transistor configuration, the amount of metal silicide within the drain and source regions 114, wherein, however, for advanced applications, the depth of the metal silicide regions 117, although highly desirable in the gate electrode 115, may not be significantly increased without a high risk for shorting the drain and source regions 114 with the active area 112, thereby causing a device failure. Due to the limited depth of the metal silicide region 117 in the drain and source regions 114, it is thus important to provide a high quality metal silicide within the entire area of the drain and source regions 114. In conventional approaches, however, the metal silicide at the interface between the drain and source regions 114 and the trench isolation structure 114, indicated as 113A, may have a reduced thickness, thereby reducing the efficiency of the metal silicide, since, in total, a moderately large area (see FIG. 1b) may suffer from a reduced metal silicide thickness.
The present disclosure is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.